1. Technical Field
The present invention relates in general to caches in data processing systems and in particular to cache directory addressing and parity checking schemes for caches. Still more particularly, the present invention relates to a cache directory addressing and parity checking scheme which reduces the data storage size for caches in data processing systems.
2. Description of the Related Art
Contemporary data processing systems commonly employ caches for staging data from system memory to the processor(s) with reduced access latency. Such caches typically employ a parity checking mechanism within the cache directory. FIG. 3 depicts a cache directory addressing and parity checking scheme for a 32 bit data processing system using a 1 MB. The 1 MB cache directory addressing configuration employs a 64 byte cache line. A cache line is the block of memory which a coherency state describes, also referred to as a cache block. When addressing the cache, bits 26-31 (6 bits) of the address specify an intra-cache line address, bits 12-25 (14 bits) of the address are utilized as an index to cache lines in the cache directory and the cache memory, and bits 0-11 (12 bits) of the address utilized as the cache line address tag. The intra-cache line address field allows a particular byte to be selected from a cache line. The index field specifies a row (or congruence class) within the cache directory and memory. The address tag field also identifies a particular cache line. The address tag is stored within the cache directory entry corresponding to the cache line containing the data associated with the address. Matching the address tag field of an address to the contents of a cache directory entry verifies that the correct cache entry is being selected.
In the known art, an address index field (address bits [12-25]) is utilized by cache directory 302 to select a entry 302a within cache directory 302. The address index field maps to address lines 0-13 of cache directory 302 and cache memory (not shown). The selected cache directory entry 302a contains a 12-bit address tag 302b and a parity bit 302c. Parity bit 302c within cache directory entry 302a contains the parity of address tag 302b. Address tag 302b is passed to comparator 304 for comparison with the address tag field (address bits [0-11]) of an address presented. Address tag 302b and parity bit 302c are passed together to parity checking logic 306 to verify address tag 302b. Parity checking logic 306 computes the parity of address tag 302b and compares the result with parity bit 302c, generating a signal 308 indicating whether a match is detected.
One problem with the approach to implementing a cache directory addressing and parity checking system of the type described above is the additional cache directory space required to associate a parity bit with address tags in each cache entry. It would be desirable, therefore, to provide a cache directory addressing and parity checking scheme which did not require parity bit storage in the cache directory. It would further be advantageous if the cache directory addressing and parity checking scheme utilized did not require novel parity generation and/or checking logic. It would further be advantageous for the mechanism to improve delay within critical cache directory access paths.